Our Services
Physical Design (PD)
- Logic/Physical Synthesis
- IO ring preparation & Bump planning
- Timing Constraints Preparation and Validation
- Floorplan & power planning
Static Timing Analysis (STA)
- Process Variation and related Margins
- Peripheral Interface protocols and timing
- Mission mode and Test mode Constraints
- High Speed Clocking Architecture
Physical Verification (PV)
- Design Rule Check (DRC)
- Base & Metal DRC
- Layout versus Schematic (LVS)
- Electrical Rule Check (ERC)
Analog Layout
- Experience down to 7nm process node
- Floor planning & Area optimization
- Analog layout matching/shielding techniques
- IR drop and EM analysis
Design Verification (DV)
- Understanding the design specification
- Complete verification environment
- Gate level simulations
- Advanced IP & SoC Verification
